Digital Physical Design Engineer (Place & Route)

  • Huawei Technologies Ltd.
  • Ottawa, ON, Canada
  • May 20, 2018
Data & Analytics Engineering Health Care

Job Description

Digital Physical Design Engineer (Place & Route)

Our Team

Our team provides leading edge serial interface (SerDes) solutions to Huawei worldwide. Join one of the strongest and most successful SerDes development teams in the world and largest mixed signal IC design team in Canada. Work in an enthusiastic and motivated environment on the bleeding edge of technology. Enjoy unlimited access to latest CMOS nodes and HW and SW development tools.

Position Overview
In this role, you will be working as a Physical Design Engineer (Place & Route ) in a team environment performing full-custom analog and mixed-signal layout of next generation high-speed interfaces and signal integrity systems (aka SerDes, PHY, HSS, wireline transceivers, optical transceivers) in deep submicron FinFET technologies. Multiple positions are available in Toronto or Ottawa Design Centers at different seniority levels depending on candidate qualifications.


You will be responsible for floor planning, and both block-level and top-level P&R of digital and mixed signal IC. You will put into action your solid understanding of advanced technologies and STA fundamentals to create high-quality high-speed digital physical designs. You will utilize your strong experience in deep submicron CMOS and FinFET technologies. You will be responsible for physical implementation from netlist to GDS of large, complex, high-performance CMOS chips, including PnR, timing analysis, PI/SI analysis, physical verification, DFR design and verification, DFM design and verification, physical design data delivery.


  • MASc or BASc in Electrical Engineering or equivalent degree

  • 5+ years of relevant experience in P&R and physical design

  • Must have direct experience in deep submicron FinFET CMOS (16nm or below)

  • Experience in FinFET technologies is a must

  • Experienced in synthesis, Place & Route, timing closure, PV, PI, PPA improvement .etc and major EDA tools including Cadence, Synopsys and Mentor tools

  • 3. A solid understanding of synthesis, timing driven layout and post-layout timing analysis of deep sub-micron designs is essential.

  • 4. Must be a self starter and be able to independently drive task to completion. Must be an effective team player with good communication skills.

  • Experience in tcl/perl/shell/python programming, Mentor Calibre DRC/LVS/PERC, and Apache Totem EM & IR analysis is a plus

  • Experience in layout lead roles and top-level layout integration is an asset

  • Experience in high-speed analog layout is an asset

Compensation Package Highlights

  • Competitive Salary, Bonuses, and Group R.R.S.P
  • Comprehensive Beenfits Packages – (Dental, Vision, and Medical)
  • Short and Long-term Disability Insurance
  • Relocation Assistance