Our team provides leading edge serial interface (SerDes) solutions to Huawei worldwide. Join one of the strongest and most successful SerDes development teams in the world and largest mixed signal IC design team in Canada. Work in an enthusiastic and motivated environment on the bleeding edge of technology. Enjoy unlimited access to latest CMOS nodes and hardware and software development tools.
In this role, you will be working as a Senior Digital Designer in a team environment conducting research and development into next generation high-speed interfaces and signal integrity systems (aka SerDes, PHY, HSS, wireline transceivers, optical transceivers) in deep submicron FinFET technologies. Multiple positions are available in Toronto or Ottawa Design Centers at different seniority levels (Senior to Principal) depending on candidate’s qualifications.
You will be responsible for the design of digital/mixed signal ASICs and providing technical insight and proposals related to system architecture. You will capitalize on your experience developing system/block level micro-architecture of PHY/DSP, PCS and other high performance digital circuits. You will participate in all phases of ASIC design from specification, design, verification, physical implementation and silicon validation. Key activities include interpreting high-level design architecture and creating detailed design specifications, generating RTL, providing timing constraints or behavioral modeling of complex analog functions, performing block/top level simulations or mixed-signal simulation of analog/digital circuits, partnering with Physical Design and DFT engineers to ensure the physically correct implementation and DFT compliance for ASIC integration and releasing IP deliverables.
- B.Sc in Electrical/Computer Engineering or Equivalent degree. M.Sc and above preferred.
- 4 yrs + of relevant experience in Digital Design
- Experience in deep submicron CMOS (65nm or below)
- Experience in low power design. Custom/Semi-custom digital implementation for low power/high-performance will be considered an advantage
- Experience in 3 or more of the following: functional/digital specification, RTL, Synthesis, STA, DFx
- Recent hands on experience with Synopsys and Cadence tools and environment: Design Compiler, Prime Time, NC-Verilog, SpyGlass and etc.
- Experience in Matlab + Simulink, DSP and FEC design will be considered an advantage
- Good scripting skills (Perl, Tcl, make and etc) is a plus
- Familiar with IP release flow and generating deliverables is a plus