Senior Verification engineer

  • Rianta Solutions Inc.
  • Ottawa, ON, Canada
  • Dec 18, 2017
Engineering

Job Description

Position will require environment development for complex system functional verification. Debug both functional and environmental errors in the RTL using simulation and debugging tools. An in-depth understanding of verification architectures and HDL/logical design are required.

Responsibilities include:

  • Develop automated regression infrastructure setup for functional verification of high complexity ASIC and SoC designs
  • Develop and use constrained-random transactors to validate functionality of system designs
  • Debug regression fails at the RTL and gate levels

Qualifications:

  • Directed and constrained-random functional test environment development and usage
  • Experience with functional/power/performance verification using simulation and emulation environments
  • Creation of test plans for complex IPs
  • Development of test benches in OVM/UVM/VMM, SystemVerilog and/or C++
  • Application of applying pseudo-random test generators
  • Development of System Verilog/C/assembly tests
  • Coverage analysis techniques

Desired Knowledge

  • Verilog, SystemVerilog, Specman e Perl, C/C++
  • 7-10 years of hands-on verification experience
  • Direct experience with OVM/UVM or VMM simulation environments
  • Knowledge of computer and peripheral architectures
  • Knowledge of networking and processor protocols – Ethernet, PCIe, Interlaken, SATA, USB, DDR