Junior Verification engineer

  • Rianta Solutions Inc.
  • Ottawa, ON, Canada
  • Dec 18, 2017

Job Description

Position will require environment development for complex system functional verification. Debug both functional and environmental errors in the RTL using simulation and debugging tools.

Responsibilities include:

  • Develop and use constrained-random transactors to validate functionality of system designs
  • Debug regression fails at the RTL and gate levels


  • Directed and constrained-random functional test environment development and usage
  • Creation of test plans
  • Application of applying pseudo-random test generators
  • Development of System Verilog/C/assembly tests
  • Coverage analysis techniques

Desired Knowledge

  • 1-3 years of hands-on verification experience
  • Direct experience with OVM/UVM or VMM simulation environments is a plus
  • Knowledge of computer and peripheral architectures is a plus
  • Knowledge of networking protocols –Ethernet, PCIe or DDR is a plus